The present invention relates to digitally programmable phase shifters and, more particularly, to a novel programmable phase shifter having a phase-shifted output at which a signal appears with synchronously switched phase, with respect to a reference-phase output.
It is often required that a signal having a referenced phase be phase shifted to provide a second signal of identical frequency and having a phase different from the first signal, which phase difference, or phase shift, can be not only programmably selected in a "random" fashion, but also wherein switching between various amounts of phase shift can be achieved in synchronous manner whereby erroneous transients are not generated in the phase-shifted output signal.
A number of techniques are known in the prior art for providing an output signal having a phase shifted from the phase of a reference signal. In particular, digital signals may be phase-shifted by means of a count-down chain wherein the count is either inhibited or advanced by one count in order to change the phase respectively in a lagging or leading direction. In this count-down-chain phase-shifter, a constant clock frequency train of pulses at the input to the circuit has an extra clock pulse "stuffed" into the clock pulse train in order to advance the count, whereby the maximum possible average clock rate usable with this form of phase shifter is reduced to about one-half the clock rate of the counter utilized for counting the clock pulse train. This reduction in maximum average clock rate is required so that the "stuffed" pulse will still satisfy the timing specifications of the clock pulse counter. This reduction in maximum average clock rate limits the number of phase increments which may be achieved at a given output frequency. If the "stuffed" pulse technique is not utilized, phase changes are limited to changes in the lagging direction only. Phase shifters using a count-down chain require that the total phase change be created by summation of the required number of incremental phase changes whereby the time required to realize a desired phase change, equal to K incremental phase changes, is equal to the time required to implement the minimum phase change K times, and further limits the maximum frequency of phase-shift operations. It is therefore desirable to implement a phase shifter of the programmable type, which does not require the addition, or "stuffing", of one or more extra clock pulses and subsequently allows the phase-shift circuitry to operate at the maximum specified frequency of the logic components thereof, thereby achieving a minimum possible phase step increment, and hence the maximum number of programmable phase increments, for a given output frequency. It is also desirable that the amount of phase shift can be programmed in a random manner so that any desirable phase relationship can be programmed with a single change in the phase shift control data to the circuitry. It is also desirable that the operation of the phase shift circuit be synchronous with a common phase-shift circuitry clock signal, whereby problems with so-called "gating slivers" may be avoided.